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TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 1 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y features ! single chip solution with only a few external components ! stand-alone fixed-frequency transceiver operation modes ! programmable multi-channel transceiver operation modes ! low current consumption in active mode and very low standby current ! pll-stabilized rf vco (lo) with internal varactor diode ! lock detection in programmable channel applications ! 3wire bus serial control interface ! fsk/ask modulation selection ! fsk for digital data and fm for analog signal reception ! rssi allows signal strength indication and ask detection ! switchable lna gain for improved dynamic range ! automatic pa turn-on after pll lock ! fm possible with external varactor ! ask modulation achieved by on/off keying ! afc option for extended input frequency acceptance range ! surface mount package lqfp32 ordering information part no. (engineering samples) temperature code package code TH7120 (TH7120-03) e (-40 c to 85 c) ne (lqfp32) application examples ! general bi-directional half duplex digital data transmission or analog signal transmission ! low-power telemetry ! alarm and security systems ! keyless car and central locking ! domotics ! model control technical data overview ! frequency range: 300 mhz to 930 mhz for programmable channel applications ! 315 mhz, 433 mhz, 868 mhz or 915 mhz fixed-frequency single-channel variants ! power supply range: 2.5 v to 5.5 v ! temperature range: -40 c to +85 c ! standby current: 50 na ! operating current: 6.0 ma in receive mode at low gain ! operating current 9.0 ma in transmit mode at 0 dbm output power ! adjustable output power range from ?15 dbm to +6 dbm ! sensitivity: -103 dbm at fsk with 150 khz if filter bw ! sensitivity: -105 dbm at ask with 150 khz if filter bw ! maximum data rate for fsk and ask: 60 kbit/s nrz ! maximum input level: ?10 dbm at fsk and -20 dbm at ask ! input frequency acceptance: 50 khz (with afc option) ! frequency deviation range: 5 khz to 100 khz ! maximum analog modulation frequency: 20 khz ! 3 mhz to 12 mhz crystal reference
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 2 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y general description the TH7120 is a single chip fsk/fm/ask transceiver ic. it is designed to operate in low-power multi-channel programmable or single-channel stand-alone, half-duplex data transmission systems. it can be used for ism, srd or any other application operating in the frequency ranging of 300 mhz to 930 mhz. the TH7120 transceiver ic consists of the following building blocks: " low-noise amplifier (lna) for high-sensitivity rf signal reception with switchable gain " mixer (mix) for rf-to-if down-conversion " if amplifier (ifa) to amplify and limit the if signal and for rssi generation " phase-coincidence demodulator with external ceramic discriminator (fsk demodulator) " operational amplifier, connected to demodulator output (oa1) " operational amplifier, integrator circuit at fsk-afc mode (oa2) " control logic with 3wire bus serial control interface (sci) " reference oscillator (ro) with external crystal " reference divider (r counter) " programmable divider (n/a counter) " phase-frequency detector (pfd) " charge pump (cp) " voltage control oscillator (vco) with internal varactor " power amplifier (pa) with adjustable output power the transceiver can be used either as a 3wire-bus-controlled programmable or as a stand-alone fixed- frequency device. after power up, the transceiver is set to fixed-frequency mode. in this mode, pins fs0/sden and fs1/ld must be connected to v ee or v cc in order to set the desired frequency of operation. the logic levels at pins fs0/sden and fs1/ld must not be changed after power up in order to remain in fixed-frequency mode. channel frequency 433.92 mhz 868.3 mhz 315.0 mhz 915.0 mhz fs0/sden 1010 fs1/ld 0011 after the first logic level change at pin fs0/sden, the transceiver enters into programmable mode while pin fs1/ld is now a pll lock detector output. in this mode, the user can set any pll frequency or mode of op- eration by the sci. in the fixed-frequency mode, the user can set the transceiver to standby, receive, transmit or idle (only pll synthesizer active) mode via control pins re/sclk and te/sdta. operation mode standby receive transmit idle re/sclk 0101 te/sdta 0011
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 3 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y block diagram figure 1: TH7120 block diagram in_lna lna gain_lna out_lna in_mix out_dta oa2 bias if mix out_mix1 in_ifa vee_if ifa in_dem 26 29 28 30 32 31 1 vcc_if 2 3 out_dem 6 oa1 8 int1 5 int2 4 rssi 7 1.5pf 200k vee_lna 27 mix demodulator fsk vee_pll out_pa fsk ask lo in_dta ask/fsk re/sclk te/sdta fs0/sden 25 vcc_pll 20 ps_pa 24 fsk_sw fs1/ld vee_ro 11 19 9 17 16 15 13 12 ro ro r counter n counter ro 10 lf 21 sclk sdta sden control logic sci tnk_lo 23 vco 22 pa 18 vee_dig 14 vcc_dig
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 4 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y pin definition and description pin no. name i/o type functional schematic description 1 in_ifa input 3.1k 3.1k in_ifa 1 vcc 140a vee 2.2k if amplifier input, approx. 2 k ? single-ended 2 vcc_if supply positive supply of lna, mix, ifa, fsk demodulator, pa, oa1 and oa2 3 in_dem analog i/o vcc 100a 10a vee in_dem 3 77k 1.5p if amplifier output and de- modulator input, connection to external ceramic discrimi- nator 4 int2 output integrator output oa2 8 out_dta output vcc vee int2 4 8 out_dta output oa1 5 int1 input inverting inputs oa1 and oa2 6 out_dem analog i/o oa2 bias vee vcc int1 5 vee out_dem 6 vcc 120 120 vee vcc 120 10.5p 10.5p 520k 520k 1k oa1 + 200k demodulator output and non- inverting input oa1 7 rssi output vcc vee rssi 7 120 vee vcc 5a 5a rssi output
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 5 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y pin no. name i/o type functional schematic description 9 vee_ro ground ground of ro 10 ro analog i/o 40p vee vcc ro 10 2.6a 39k 40p ro input, base of bipolar transistor 11 fsk_sw analog i/o vcc vee fsk_sw 11 fsk pulling pin, switch to ground or open 12 in_dta input ask/fsk modulation data input, pull down resistor 120k ? 15 re/sclk input receiver enable input / clock input for the shift register, pull down resistor 120k ? 16 te/sdta input vee vcc in_dta 12 re/sclk 15 16 te/sdta 120k 120 transmitter enable input / serial data input, pull down resistor 120k ? 13 ask/fsk input ask/fsk mode select input 17 fs0/sden input vee vcc ask/fsk 13 17 fs0/sden 120 frequency select input / se- rial data enable input 14 vcc_dig supply positive supply of serial port and control logic 18 vee_dig ground ground of serial port and control logic 19 fs1/ld input vee vcc fs1/ld 19 120 frequency select input / lock detector output 20 vcc_pll supply positive supply of pll fre- quency synthesizer 22 vee_pll ground ground of pll frequency synthesizer
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 6 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y pin no. name i/o type functional schematic description 21 lf analog i/o charge pump output, con- nection to external loop filter 23 tnk_lo analog i/o 120 10k 6.3p vcc vcc vcc vee 33 33 vee lf 21 tnk_lo 23 vco open-collector output, connection to external lc tank 24 ps_pa analog i/o vee vee vcc vcc 120 ps_pa 24 power-setting input 25 out_pa output vee vee vcc out_pa 25 power amplifier open- collector output 27 vee_lna ground ground of lna and pa 28 out_lna output lna open-collector output, connection to external lc tank at rf 26 in_lna input 40p vee vee 3.8k out_lna 28 bias 37 in_lna 26 lna input, approx. 50 ? single-ended 29 gain_lna input vcc vee gain_lna 29 120 lna gain control input
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 7 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y pin no. name i/o type functional schematic description 30 in_mix input vcc 210 bias lo in_mix 30 vee vee mixer input, approx. 200 ? single-ended 31 vee_if ground ground of ifa, demodulator, oa1 and oa2 32 out_mix output vcc vee out_mix 32 100 mixer output, approx. 330 ? single-ended
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 8 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y stand-alone fixed-frequency operation after power up the transceiver is set to fixed-frequency mode. in this mode, pins fs0/sden and fs1/ld must be connected to v ee or v cc to set the desired frequency of operation. the logic levels at pins fs0/sden and fs1/ld must not be changed after power up in order to remain in fixed-frequency mode. the default settings of the control word bits in stand-alone mode are described in the frequency selection table. frequency selection channel frequency 433.92 mhz 868.3 mhz 315 mhz 915 mhz fs0/sden 1010 fs1/ld 0011 reference oscillator frequency 7.1505 mhz r counter ratio in rx mode 16 16 18 30 pfd frequency in rx mode 446.91 khz 446.91 khz 397.25 khz 238.35 khz n/a counter ratio in rx mode 947 1919 766 3794 vco frequency in rx mode 423.22 mhz 857.60 mhz 304.30 mhz 904.30 mhz rx frequency 433.92 mhz 868.30 mhz 315.00 mhz 915.00 mhz r counter ratio in tx mode 16 16 18 30 pfd frequency in tx mode 446.91 khz 446.91 khz 397.25 khz 238.35 khz n/a counter ratio in tx mode 971 1943 793 3839 vco frequency in tx mode 433.92 mhz 868.30 mhz 315.00 mhz 915.00 mhz tx frequency 433.92 mhz 868.30 mhz 315.00 mhz 915.00 mhz if frequency in rx mode 10.7 mhz 10.7 mhz 10.7 mhz 10.7 mhz
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 9 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y default register settings after power-up bits a-word symbols channel ?00? 868.3 mhz channel ?01? 433.92 mhz channel ?10? 915.0 mhz channel ?11? 315.0 mhz b-word symbols channel ?00? 868.3 mhz channel ?01? 433.92 mhz channel ?10? 915.0 mhz channel ?11? 315.0 mhz 21 not used 0 not used 0 20 di_mode 0 not used 0 19 modul 0 endelpll 1 18 highcur 0 lnahyst 1 17 lock_mode 0 enadj 0 16 pa_auto 0 enfm 0 15 pow1 1 max2 1 14 pow0 1 max1 1 13 mixg 1 max0 1 12 lnag 1 min2 0 11 te 0 min1 1 10 re 0 min0 1 9 rr9 0 0 0 0 rt9 0 0 0 0 8 rr8 0 0 0 0 rt8 0 0 0 0 7 rr7 0 0 0 0 rt7 0 0 0 0 6 rr6 0 0 0 0 rt6 0 0 0 0 5 rr5 0 0 0 0 rt5 0 0 0 0 4 rr4 1 1 1 1 rt4 1 1 1 1 3 rr3 0 0 1 0 rt3 0 0 1 0 2 rr2 0 0 1 0 rt2 0 0 1 0 1 rr1 0 0 1 1 rt1 0 0 1 1 0 rr0 0 0 0 0 rt0 0 0 0 0 bits c-word symbols channel ?00? 868.3 mhz channel ?01? 433.92 mhz channel ?10? 915.0 mhz channel ?11? 315.0 mhz b-word symbols channel ?00? 868.3 mhz channel ?01? 433.92 mhz channel ?10? 915.0 mhz channel ?11? 315.0 mhz 21 lnagi_e 0 modul_ctr 0 20 polar 0 ld_tm1 1 19 high2 0 0 0 0 ld_tm0 0 18 high1 1 1 1 1 er_tm1 0 17 up 1 0 1 0 er_tm0 0 16 nr16 0 0 0 0 nt16 0 0 0 0 15 nr15 0 0 0 0 nt15 0 0 0 0 14 nr14 0 0 0 0 nt14 0 0 0 0 13 nr13 0 0 0 0 nt13 0 0 0 0 12 nr12 0 0 0 0 nt12 0 0 0 0 11 nr11 0 0 1 0 nt11 0 0 1 0 10 nr10 1 0 1 0 nt10 1 0 1 0 9 nr9 1 1 1 1 nt9 1 1 1 1 8 nr8 1 1 0 0 nt8 1 1 0 1 7 nr7 0 1 1 1 nt7 1 1 1 0 6 nr6 1 0 1 1 nt6 0 1 1 0 5 nr5 1 1 0 1 nt5 0 0 1 0 4 nr4 1 1 1 1 nt4 1 0 1 1 3 nr3 1 0 0 1 nt3 0 1 1 1 2 nr2 1 0 0 1 nt2 1 0 1 0 1 nr1 1 1 1 1 nt1 1 1 1 0 0 nr0 1 1 0 0 nt0 1 1 1 1
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 10 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y programmable channel operation serial control interface description a 3-wire (sclk, sdta, sden) serial control interface (sci) is used to program the transceiver in multi- channel mode (see fig. 2). at each rising edge of the sclk signal, the logic value on the sdta pin is written into a 24-bit shift register. the data stored in the shift register are loaded into one of the 4 appropriate latches on the rising edge of sden. the control words are 24 bits lengths: 2 address bits and 22 data bits. the first two bits (bit 23 and 22) are latch address bits. as additional leading bits are ignored, only the least significant 24 bits are serial-clocked into the shift register. the first incoming bit is the most significant bit (msb). to program the transceiver in multi-channel application, four 24-bit words may be sent: a-word, b-word, c-word and d-word. if individual bits within a word have to be changed, then it is sufficient to program only the appro- priate 24-bit word. the serial data input timing and the structure of the control words are illustrated in fig. 2 and 3. table register settings describes the function of each bit. figure 2: sci block diagram due to the static cmos design, the sci consumes virtually no current and it can be programmed in active as well as in standby mode. figure 3: serial data input timing t eh t ew t es t cwh t cwl t ch t cs bit 22 bit 1 bit 0 bit 23 data invalid lsb msb sdta sclk sden data invalid a - latch addr decoder b - latch c - latch d - latch 22 a-word 22 22 ?? 00 ?? 10 ?? 11 ?? 01 2 22 22 22 22 b-word 22 d-word 22 c-word 24-bit shift register sden sdta sclk
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 11 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y sci words a-word msb ls b 23222120191817161514131211109876543210 00 xxxxxxxxxxxxxxxxxxxxxx addr not used di_mode modul highcur lock_mode pa_auto pow1 pow0 mixg lnag te re rr9 rr8 rr7 rr6 rr5 rr4 rr3 rr2 rr1 rr0 b-word msb ls b 23222120191817161514131211109876543210 01 xxxxxxxxxxxxxxxxxxxxxx addr not used not used endelpll lnahyst enadj enfm max2 max1 max0 min2 min1 min0 rt9 rt8 rt7 rt6 rt5 rt4 rt3 rt2 rt1 rt0 c-word msb ls b 23222120191817161514131211109876543210 10 xxxxxxxxxxxxxxxxxxxxxx addr lnagi_e polar high2 high1 up nr16 nr15 nr14 nr13 nr12 nr11 nr10 nr9 nr8 nr7 nr6 nr5 nr4 nr3 nr2 nr1 nr0 d-word msb ls b 23222120191817161514131211109876543210 11 xxxxxxxxxxxxxxxxxxxxxx addr modul_ctr ld_tm1 ld_tm0 er_tm1 er_tm0 nt16 nt15 nt14 nt13 nt12 nt11 nt10 nt9 nt8 nt7 nt6 nt5 nt4 nt3 nt2 nt1 nt0
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 12 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y register settings a-word symbol bits no. description software button rr9:rr0 rr9:rr0 [9:0] 10 reference divider ratio in rx mode te:re [11:10] 2 select active mode at programmable-channel application: opmode ?00? ?11? ?10? ?01? standby mode idle mode transmit mode receive mode lnag [12] 1 select lna gain at internal gain control: lnagain ?0? ?1? low lna gain high lna gain mixg [13] 1 select mixer conversion gain at programmable-channel application: mixgain ?0? ?1? low gain high gain pow1:pow0 [15:14] 2 select output power at programmable-channel application: txpower ?00? ?01? ?10? ?11? p max - 20 dbm p max - 12 dbm p max - 6 dbm p max pa_auto [16] 1 disable automatic pa turn-on after pll lock: pa_auto ?0? ?1? enabled disabled lock_mode [17] 1 select pfd output analyse mode of lock detecting: lock_mode ?0? ?1? before lock only before and after lock. highcur [18] 1 select charge pump output current: cpcur ?0? ?1? 260 a 1300 a modul [19] 1 select modulation mode at internal modulation control: ask/fsk ?0? ?1? ask fsk di_mode [20] 1 select mode for input data: ?0? normal di_mode ?0? for space at ask or f min at fsk, ?1? for mark at ask or f max at fsk ?1? inverse ?1? for space at ask or f min at fsk, ?0? for mark at ask or f max at fsk not used [21] 1 ?x?
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 13 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y b-word symbol bits no. description software button rt9:rt0 rt9:rt0 [9:0] 10 reference divider ratio in tx mode min2:min0 [12:10] 3 select minimum value of ro active current: romin ?000? ?001? ?010? ?011? ?100? ?101? ?110? ?111? 0 a 50 a 100 a 150 a 200 a 250 a 300 a 350 a max2:max0 [15:13] 3 select maximum value of ro active current: romax ?000? ?001? ?010? ?011? ?100? ?101? ?110? ?111? 0 a (ro is off) 50 a 100 a 150 a 200 a 250 a 300 a 350 a enfm [16] 1 test bit. forced '0' for correct functioning. enadj [17] 1 test bit. forced '0' for correct functioning. lnahyst [18] 1 enable lna hysteresis: lnahyst ?1? ?0? disabled enabled endelpll [19] 1 enable delayed start of the pll: endelpll ?1? ?0? disabled enabled. not used [20] 1 ?x? not used [21] 1 ?x?
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 14 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y c-word symbol bits no. description software button nr16:nr0 nr16:nr0 [16:0] 17 feedback divider ratio in rx mode up [17] 1 select frequency band: band ?1? ?0? up to 500 mhz 500 to 1000mhz high2:high1 [19:18] 2 select vco active current: vcocur ?00? ?01? ?10? ?11? low current (250 a) standard current (350 a) high1 current (450 a) high2 current (550 a) polar [20] 1 select phase detector polarity: pfdpol ?1? ?0? positive (1) negative (2) (2) (1) frequency output vco vco input voltage lnagi_e [21] 1 select lna gain control mode: lnactrl ?0? ?1? external lna gain control internal lna gain control
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 15 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y d-word symbol bits no. description software button nt16:nt0 nt16:nt0 [16:0] 17 feedback divider ratio in tx mode er_tm1:er_tm0 [18:17] 2 select maximum enabled pfd output error for lock detecting (in reference frequency clocks): er_tm1:er_tm0 ?00? ?01? ?10? ?11? 2 clocks 4 clocks 8 clocks 16 clocks ld_tm1:ld_tm0 [20:19] 2 select minimum number of pfd reference frequency clocks before lock detecting: ld_tm1:ld_tm0 ?00? ?01? ?10? ?11? 4 clocks 16 clocks 64 clocks 256 clocks modul_ctr [21] 1 select mode of modulation control: modctrl ?0? ?1? external modulation control internal modulation control
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 16 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y technical data absolute maximum ratings parameter symbol condition / note min max unit supply voltage v cc 0 7.0 v input voltage v in - 0.3 v cc +0.3 v input current i in -1 1 ma input rf level p imax no damage 10 dbm storage temperature t stg -40 +125 c electrostatic discharge v esd1 human body model, 1) -1.0 +1.0 kv electrostatic discharge v esd2 human body model, 2) tbd tbd kv 1) pins in_dta, ask/fsk, re/sclk; te/sdta, fs0/sden, fs1/ld 2) all pins, exept in_dta, ask/fsk, re/sclk; te/sdta, fs0/sden, fs1/ld normal operating conditions parameter symbol condition min max unit supply voltage v cc 2.5 5.5 v operating temperature t a -40 +85 oc carrier frequency f c 300 930 mhz vco frequency f vco 300 930 mhz ro frequency f ro 312mhz frequency deviation ? f at fm or fsk 5 120 khz fsk data rate r fsk nrz 60 kbit/s fm bandwidth f m 20 khz ask data rate r ask nrz 60 kbit/s dc characteristics all parameters under normal operating conditions, unless otherwise stated; typical values at t a = 23 c and v cc = 3 v parameter symbol condition min typ max unit standby current i sby te/sdta=0, re/sclk=0 50 100 na idle current i idle te/sdta=1, re/sclk=1 @ f i = 433.92 mhz 2.5 3.2 ma total supply current in receive mode at low gain i rx_low te/sdta=0, re/sclk=1 v gain_lna > 1.4 v @ f i = 433.92 mhz 6.0 8.0 ma total supply current in receive mode at high gain i rx_high te/sdta=0, re/sclk=1 v gain_lna < 0.8 v @ f i = 433.92 mhz 7.0 9.0 ma total supply current in transmit mode at 0 dbm power i tx_0 te/sdta=1, re/sclk=0 ask/fsk=1 @ f i = 433.92 mhz, @ p o = 0 dbm 9.0 11.5 ma
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 17 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y ac system characteristics of the receiver part all parameters under normal operating conditions, unless otherwise stated; all parameters based on test circuits for fsk (fig. 4 to 5), fm and ask (fig. 6 to 7), respectively; rf at 433.92 mhz parameter symbol condition min typ max unit input sensitivity ? fsk p min_fsk b if = 150khz ? f = 50 khz (fsk/fm) ber 3 ? 10 -3 -103 dbm input sensitivity ? ask p min_ask b if = 150khz ber 3 ? 10 -3 -105 dbm maximum input signal ? fsk/fm at low gain p max_fsk_1 ber 3 ? 10 -3 v gain_lna > 1.4 v 10 dbm maximum input signal ? fsk/fm at high gain p max_fsk_0 ber 3 ? 10 -3 v gain_lna < 0.8 v -10 dbm maximum input signal ? ask at low gain p max_ask_1 ber 3 ? 10 -3 v gain_lna > 1.4 v -20 dbm maximum input signal ? ask at high gain p max_ask_0 ber 3 ? 10 -3 v gain_lna < 0.8 v 0dbm image rejection ? p imag tbd db blocking immunity ? p block ? f block > 2mhz, note 1 tbd db start-up time ? fsk/fm t fsk te/sdta=0, re/sclk=1 valid data at output 1ms start-up time ? ask t ask depends on ask de- tector time constant and start-up mode, valid data at output t fsk + 200k * c6 ms spurious emission p spur -70 dbm notes: 1. desired signal with fsk/fm or ask modulation, cw blocking signal ac system characteristics of the transmitter part all parameters under normal operating conditions, unless otherwise stated; typical values at t a = 23 c and v cc = 3 v; te/sdta=1, re/sclk=0, ask/fsk=1, rps 15 k ? , f c = 433.92 mhz, test circuit shown in fig. 4 to 7 parameter symbol condition min typ max unit output power p o cw mode 4 6 8 dbm fsk deviation ? f fsk depends on c x1 , c x2 and crystal parameter 5 50 100 khz data rate fsk r fsk 60 kbit/s fm deviation ? f fm adjustable with varactor and v fm 6 khz modulation frequency fm f mod 5khz data rate ask r ask 60 kbit/s pll spurs emission p spur at all f c and nominal p o -36 dbm harmonic emission p harm at all f c and power steps - -36 dbm vco gain k vco 35 mhz/v charge pump current i cp 260 a start-up time t tx from ?standby? to ?transmit? mode 1ms
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 18 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y output power selection typical values at t a = 23 c and v cc = 3 v: te/sdta = 1, re/sclk = 0, ask/fsk = 1, f c = 433.92 mhz, cw mode rps / k ? ? ? ? 15 k 6.8 k 3.3 k 1.0 k i cc / ma tbd 9.0 tbd tbd p o / dbm 6 0 -6 -15 p harm / dbm -36 -36 -36 -36 serial control interface parameter symbol condition min max unit data to clock set up time f cs 150 ns data to clock hold time t ch 50 ns clock pulse width high t cwh 100 ns clock pulse width low t cwl 100 ns clock to load enable set up time t es 100 crystal parameters parameter symbol condition min max unit crystal frequency f crystal fundamental mode, at 3 12 mhz load capacitance c load 10 15 pf static capacitance c 0 7pf motional resistance r m 70 ?
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 19 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y application circuit examples programmable channel fsk application circuit figure 4: test circuit for programmable channel fsk operation sclk sdta sden lock detect fsk output fsk input cx1 cx2 cerfil xtal rps rb ctx0 c1 c2 l1 ltx0 crx0 l0 rssi out_mix vee cerres c3 cb5 c5 c4 c0 cb0 cb1 cb2 cb3 cb6 cb7 re/sclk in_dta ask/fsk fsk_sw ro vcc vee vcc fs1/ld vee lf tnk_lo out_pa in_lna out_lna vee gain_lna in_mix vee in_ifa in_dem int2 int1 rssi out_dem out_dta vcc vcc vcc vcc vcc fs0/sden cb4 rf input rf output antenna matching network cp0 rp cf1 cf2 rf
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 20 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y fixed-frequency fsk application circuit figure 5: test circuit for fixed-frequency fsk operation at 433 mhz fsk output fsk input tx enable rx enable cx1 cx2 xtal rps rb ctx0 c1 c2 l1 ltx0 crx0 l0 cerfil rssi out_mix vee cb5 c5 c4 c0 cf1 cf2 rf cb4 cb0 cb1 cb2 cb3 cb6 cb7 c3 rf input rf output antenna matching network cerres cp0 rp re/sclk in_dta ask/fsk fsk_sw ro vcc vee vcc fs1/ld vee lf tnk_lo out_pa in_lna out_lna vee gain_lna in_mix vee in_ifa in_dem int2 int1 rssi out_dem out_dta vcc vcc vcc vcc vcc fs0/sden
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 21 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y fsk test circuit component list to fig. 4 and fig. 5 part size value @ 433.92 mhz tolerance description c0 0805 0.68 pf 5% vco tank capacitor c1 0603 6.8 pf 5% lna output tank capacitor c2 0603 1 pf 5% mix input matching capacitor c3 0805 10 nf 10% data slicer capacitor c4 0805 100 pf 10% demodulator output low-pass capacitor, depending on data rate c5 0805 330 pf 10% rssi output low pass capacitor cb0 0805 100 nf 10% blocking capacitor cb1 to cb4 0805 0603 330 pf 10% blocking capacitor cb5 0603 330 pf 10% blocking capacitor cb6 0603 10 nf 10% blocking capacitor cb7 0603 330 pf 10% blocking capacitor cf1 0805 390 pf 5% loop filter capacitor cf2 0805 150 pf 5% loop filter capacitor cx1 0805 18 pf 5% ro capacitor cx2 0805 68 pf 5% ro capacitor for fsk ( ? f = 20 khz) cp0 0805 10 - 12 pf 5% cerres parallel capacitor crx0 0603 100 pf 5% rx coupling capacitor ctx0 0603 100 pf 5% tx coupling capacitor rb 0805 10 ? 10% blocking resistor for vcc rp 0805 3.9 k ? 5% cerfil parallel resistor rf 0805 47 k ? 5% loop filter resistor rps 0805 82 k ? 5% power-select resistor, only required at fixed-frequency operation l0 0805 18 nh 5% vco tank inductor l1 0603 15 nh 5% lna output tank inductor ltx0 0805 150 nh 5% tx impedance matching inductor xtal hc49-smd 7.1505 mhz 30ppm calibr. 30ppm temp. fundamental-mode crystal, c load = 10 pf to 15pf, c 0, max = 7 pf, r m, max = 70 ? cerfil leaded type sfe10.7mfp @ b if2 = 40 khz tbd ceramic filter from murata smd type sfecv10.7mjs-a @ b if2 = 150 khz 40 khz ceramic filter from murata cerres smd type cdacv10.7mg18-a ceramic demodulator tank from murata notes: ? nip ? not in place, may be used optionally ? antenna matching network according to evaluation board description evb7120
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 22 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y programmable channel ask application circuit figure 6: test circuit for programmable channel ask operation ask output ask input cx1 cerfil xtal rps rb ctx0 c1 c2 l1 ltx0 crx0 l0 rssi out_mix vee c3 cb5 c5 c0 cb0 cb1 cb2 cb3 cb6 cb7 re/sclk in_dta ask/fsk fsk_sw ro vcc vee vcc fs1/ld vee lf tnk_lo out_pa in_lna out_lna vee gain_lna in_mix vee in_ifa in_dem int2 int1 rssi out_dem out_dta vcc vcc vcc vcc vcc sclk sdta sden lock detect fs0/sden rf input rf output antenna matching network cf1 cf2 rf
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 23 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y fixed-frequency ask application circuit figure 7: test circuit for fixed-frequency ask operation at 433 mhz ask output ask input tx enable rx enable cx1 cerfil xtal rps rb ctx0 c1 c2 l1 ltx0 crx0 l0 rssi out_mix vee c3 cb5 c5 c0 cb0 cb1 cb2 cb3 cb6 cb7 re/sclk in_dta ask/fsk fsk_sw ro vcc vee vcc fs1/ld vee lf tnk_lo out_pa in_lna out_lna vee gain_lna in_mix vee in_ifa in_dem int2 int1 rssi out_dem out_dta vcc vcc vcc vcc vcc fs0/sden rf input rf output antenna matching network cf1 cf2 rf
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 24 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y ask test circuit component list to fig. 6 and fig. 7 part size value @ 433.92 mhz tolerance description c0 0805 nip 5% vco tank capacitor c1 0603 6.8 pf 5% lna output tank capacitor c2 0603 1 pf 5% mix input matching capacitor c3 0805 10 nf 10% data slicer capacitor c5 0805 330 pf 10% rssi output low pass capacitor cb0 0805 100 nf 10% blocking capacitor cb1 to cb3 0805 0603 330 pf 10% blocking capacitor cb5 0603 330 pf 10% blocking capacitor cb6 0603 10 nf 10% blocking capacitor cb7 0603 330 pf 10% blocking capacitor cf1 0805 1.5 nf 5% loop filter capacitor cf2 0805 150 pf 5% loop filter capacitor cx1 0805 27 pf 5% ro capacitor crx0 0603 100 pf 5% rx coupling capacitor ctx0 0603 100 pf 5% tx coupling capacitor rb 0805 10 ? 10% blocking resistor for vcc rf 0805 47 k ? 5% loop filter resistor rps 0805 15 k ? 5% power-select resistor, only required at fixed-frequency operation l0 0805 18 nh 5% vco tank inductor l1 0603 15 nh 5% lna output tank inductor ltx0 0805 150 nh 5% tx impedance matching inductor xtal hc49-smd 7.1505 mhz 30ppm calibr. 30ppm temp. fundamental-mode crystal, c load = 10 pf to 15pf, c 0, max = 7 pf, r m, max = 70 ? cerfil leaded type sfe10.7mfp @ b if2 = 40 khz tbd ceramic filter from murata smd type sfecv10.7mjs-a @ b if2 = 150 khz 40 khz ceramic filter from murata notes: ? nip ? not in place, may be used optionally ? antenna matching network according to evaluation board description evb7120
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 25 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y programmable channel fsk application circuit with afc figure 8: test circuit for programmable channel fsk operation with afc circuit features ! automatic frequency control (afc) ! increases input frequency acceptance range up to rf nom 50 khz ! compensation of calibration tolerances of ceramic resonator ! compensation of temperature tolerances of ceramic resonator vd fsk output fsk input cx1 cx2 cerfil xtal rps rb ctx0 c1 c2 l1 ltx0 crx0 l0 rssi out_mix vee cerres c3 cb5 r2 c5 c4 c0 cb0 cb1 cb2 cb3 cb6 cp1 re/sclk in_dta ask/fsk fsk_sw ro vcc vee vcc fs1/ld vee lf tnk_lo out_pa in_lna out_lna vee gain_lna in_mix vee in_ifa in_dem int2 int1 rssi out_dem out_dta vcc vcc vcc vcc sclk sdta sden lock detect fs0/sden cb4 rf input rf output antenna matching network cb7 vcc cf1 cf2 rf
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 26 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y fixed-frequency fsk application circuit with afc figure 9: test circuit for fixed-frequency fsk operation at 433 mhz with afc circuit features ! automatic frequency control (afc) ! increases input frequency acceptance range up to rf nom 50 khz ! compensation of calibration tolerances of ceramic resonator ! compensation of temperature tolerances of ceramic resonator vd fsk output fsk input tx enable rx enable cx1 cx2 cerfil xtal rps rb ctx0 c1 c2 l1 ltx0 crx0 l0 rssi fs0/sden out_mix vee cerres c3 cb5 r2 c5 c4 c0 cb0 cb1 cb2 cb3 cb6 cb7 cp1 re/sclk in_dta ask/fsk fsk_sw ro vcc vee vcc fs1/ld vee lf tnk_lo out_pa in_lna out_lna vee gain_lna in_mix vee in_ifa in_dem int2 int1 rssi out_dem out_dta vcc vcc vcc vcc vcc cb4 rf input rf output antenna matching network cf1 cf2 rf
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 27 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y package dimensions fig. 7: lqfp32 (low quad flat package) all dimension in mm, coplanarty < 0.1mm e1, d1 a a1 a2 e b l e, d min 0.05 1.35 0.30 0.45 0 7.00 0.8 9.00 max 1.60 0.15 1.45 0.45 0.75 7 all dimension in inch, coplanarty < 0.004? min 0.002 0.053 0.012 0.018 0 0 .27 6 0 . 03 1 0 . 35 4 max 0.630 0.006 0.057 0.018 0.030 7 a1 a2 a b e 1 32 25 17 24 8 9 16 d d1 e1 e l
TH7120 300 to 930mhz fsk/fm/ask transceiver 3901007120 page 28 of 28 data sheet rev. 005 jan. 2002 p r e l i m i n a r y your notes important notice devices sold by melexis are covered by the warranty and patent indemnification provisions appearing in its term of sale. melexi s makes no warranty, ex- press, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the describ ed devices from patent infringe- ment. melexis reserves the right to change specifications and prices at any time and without notice. therefore, prior to design ing this product into a system, it is necessary to check with melexis for current information. this product is intended for use in normal commercial applications. applications requiring ex- tended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life- support or life-sustaining equip- ment are specifically not recommended without additional processing by melexis for each application. the information furnished by melexis is believed to be correct and accurate. however, melexis shall not be liable to recipient or any third party for any dam- ages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or ind irect, special incidental or conse- quential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data he rein. no obligation or liability to recipient or any third party shall arise or flow out of melexis? rendering of technical or other services. ? 2000 melexis gmbh. all rights reserved. for the latest version of this document. go to our website at www.melexis.com or for additional information contact melexis direct: europe and japan: all other locations: phone: +32 1361 1631 phone: +1 603 223 2362 qs9000, vda6.1 and iso14001 certified

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